Referring to FIG.2 the block diagram of the fractional loop divider 21 is shown. The detailed operation of the fractional loop divider 21 is fully described in the issued patent to Martin. Here, the operation of fractional loop divider 21 will be described to the extent necessary for understanding of the present invention. The fractional loop divider 21 is includes means for minimizing spurs generated by the fractional division operation of the fractional N-synthesizer. The desired effect is achieved by a compensating means which substantially cancels the spurs generated by the fractional division operation. The compensating means consists of data register 22, accumulators 24 and 25 with programmable inputs, a multiplexer 23, a logic control circuit 27, and an offset control circuit 26. The data register receives the fractional numerator N and offset value and the fractional denominator value D from the controller 22 of FIG. 1. The accumulator 24 comprises a clocked register with a capacity which corresponds to the fractional denominator D to which the fractional numerator N is added after each clock cycle (fd cycle). Therefore, the accumulator 24 performs a digital integration of the fractional numerator N by sequentially adding the digital representation of the modulating signal 9 in each clock cycle. Each time the accumulator capacity is reached the accumulator overflows and a carry is generated. For each clock cycle when a carry is not generated the loop divisor K counts by its programmed value. For each clock cycle that a carry is generated the modulus of the divider is increased by one. The capacity D of the accumulator is scaled such that it corresponds to a 2π radians phase addition to the loop. Therefore, the contents of the first accumulator 24 represent the instantaneous value of the difference in phase between the output frequency fout and the actual frequency. Over D cycles of the divider output, N carry pulses are produced by the accumulator and the average value of the divider modulus has a integer divider part M equal to the programmed value of the divider and a fractional part equal to N/D. Thus a non-integer value for the fractional modulus J is created. It should be noted, however, that the difference between the average divider modulus and the instantaneous fractional modulus J causes a well defined and predictable phase perturbation to the PLL. This causes predictable and well defined spurs at the output of the PLL having a fundamental frequency equal to 1/D. A second accumulator 25 to which the instantaneous contents of the accumulator 24 is summed at each cycle of the divider output. The accumulator 25 performs a digital integration of the contents of the accumulator 24. For each clock cycle in which the second accumulator capacity is reached, the divider modulus is increased by one from its programmed value. On each succeeding clock cycle, the divider modulus is decreased by one from its programmed value. The net effect on the average fractional modulus J is equal to zero since counts are always added and subtracted in pairs. This operation has the effect of differentiating the output of the accumulator 25. The phase introduced to the loop by this mechanism is equivalent to the derivative of the integral of the first accumulator 24 contents. This compensation mechanism has the effect of minimizing low frequency components of the spurious waveform and enhancing components at or near 1/2 the synthesizer reference frequency fref. This is desirable since the PLL acts as a low pass filter and attenuates the high frequency components of the wave form. The fourier analysis of the output of the synthesizer 10 shows a substantial improvement in the generated spurs. The spur improvements may be furthered by increasing the capacity of the accumulators or the value of fractional denominator D. However, the increase in the value of D is limited by the number of bits allocated to the capacity of the accumulators 24 and 25. It may be appreciated that the optimal value for the offset varies with N, D and the required application. Since the spurs generated by the fractional N-synthesizer are predictable, a computer program could be written to determine optimal values of N, D, and offset value which provide the optimum spur characteristic for any desired frequency under a specific reference frequency and channel spacing requirement. These optimal values are stored in the memory 23.

One of ordinary skill in the art will appreciate that the spur compensation only occurs for all the non-zero values of fractional numerator N. When N=0 there the phase perturbations due to the fractional division operation are nonexistent and accordingly there is no need for a fractional division operation.

Referring to FIG. 3, a block diagram showing hardware implementation of the signal processor 17 is shown. The signal processor 17 is fully described in the pending U.S. patent application serial No. 07/499,102 filed on 3/26/1990 and assigned to the assignee of the present application which is hereby incorporated by reference. The signal processor includes an accumulators 44 and 45 having parallel inputs IN, clock input, positive and negative carry outputs N and P, and C bit contents. The parallel input IN of the accumulator 44 is coupled to the output of the A/D converter 18 of FIG. 1. The accumulator 44 performs a digital integration of the modulating signal 9 by sequentially adding the digital representation of the modulating signal in each clock cycle. The accumulator 44 has a pre-set capacity. When the contents of the accumulator 44 have reached the capacity, a positive carry or a negative carry is set depending on the polarity of the modulating signal 9. The capacity of the accumulator 44 is scaled such that it corresponds to a 2π radians phase addition to the loop. The accumulator 45 performs a digital integration of the contents of the first accumulator. The contents of the accumulator 45 represent the integral of the difference in phase between the modulating signal 9 and the signal which is modulated onto the carrier by the action of the accumulator 44. The scale of the second accumulator is set by the capacity of the accumulator. Capacity in the accumulator 45 represents the equivalent to 2π radians times clock cycles, where clock cycles is a unit of time. Each time the capacity of accumulator 45 is reached, the fractional modulus J is manipulated such that its value is increased by one from its steady state value for one clock cycle, then reduced by one from its steady state value on the subsequent clock cycle. This operation has the effect of differentiating the output of the second accumulator. The phase introduced to the loop by this mechanism is equivalent to the derivative of the integral of the accumulator 44 contents. The integration and differentiation of the phase perturbation substantially decreases the spurs generated by this type of phase modulation while allowing very low frequency modulation of the output frequency even though substantially high reference frequency is utilized. In the preferred embodiment of the invention a phasor relationship is established by combining the carry outputs of the accumulators 44 and 45 via the inverters 36 and 34, D flip-flops 42 and 38, and a binary encoder 41. It may be appreciated that the phasor relationship may be arbitrarily selected to accommodate any desired application. The output of the binary encoder 41 comprises a word B which defines the phasor relationship. A binary adder 43 adds the word B to the fractional modulus J and provides the loop divisor K. From the above description it may be appreciated that the loop divisor K is a comprise an instantaneously varying integer when the fractional numerator N is a non-zero value and/or the modulating signal 9 is present.

When the output frequency fout is an integer multiple of the reference frequency fref, i.e. N=0, the instantaneous variations of loop divisor K due to modulating signal may cause spurs that are not compensated for by the fractional loop divider 21. This is because no spur compensation is provided by the fractional loop divider 21 when fractional numerator N=0.

According to the present invention, for any desired frequency output fout, the reference divisor R is varied to provide a reference frequency fref which causes the fractional numerator N to be a non-zero value so as to cause the spur compensation means of the fractional loop divider 21 to be activated. Additionally, because the generated spurs by a fractional divider are predictable the reference divisor R is selected such that the generated spurs fall below the acceptable side band noise limits of the VCO 15. The value of the reference divisor R may be easily calculated for the side band noise limits of a particular VCO by utilizing well known computer programs which predict the generated spurs for a given reference divisor.

In the preferred embodiment of the invention, the synthesizer 10 is required to operate within a frequency range of about 10 MHz to 950 MHZ which generally is the operational frequency range of a two-way radio. The channel spacing of the communication system that utilizes the frequency synthesizer 10 may comprises 25 kHz or 12.5 kHz channel spacing. Accordingly the value of reference frequency fref and fractional denominators D of the fractional loop divider 21 and the reference divider 12 must be selected such that in addition to non-zero requirement of fractional numerator N both channel spacing requirements of the synthesizer 10 are accommodated as well.