SUMMARY OF THE INVENTION:
Accordingly, it is the object of the present invention to provide a fractional N-synthesizer which compensates for spurs generated due to application of a modulating signal.

The fractional-N frequency synthesizer for providing a modulated output frequency fout comprises a synthesizer loop which includes a voltage controlled oscillator for providing the output frequency fout. The output frequency fout is equal to K* fref. A fractional loop divider divides the output frequency fout by a fractional modulus J which is equal to J= M+N/D where:

   M=integer divider

   N=fractional numerator

   D=fractional denominator.

The programmable divider compensates for the generated spurs of the frequency synthesizer when N is equal to a non-zero integer. The synthesizer also includes modulation means for varying the modulus of the fractional loop divider in accordance with a modulating signal. A reference divisor R selected to provide a reference frequency fref so as to provide a non-zero fractional numerator N.

BRIEF DESCRIPTION OF THE DRAWINGS:
FIG. 1 is a block diagram of a fractional-N frequency synthesizer with spur compensation in accordance with the present invention.

FIG. 2 is a block diagram of a fractional loop divider of the fractional-N frequency synthesizer of FIG. 1.

FIG. 3 is a block diagram of a signal processor of the fractional-N frequency synthesizer of FIG. 1

FIG. 4 is a graph of the side band noise of a voltage controlled oscillator of the fractional-N frequency synthesizer of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, block diagram of a fractional-N frequency synthesizer 10 according to the present invention is shown. The frequency synthesizer 10 utilizes well known phase locked loop (PLL) principals for generating various frequency outputs fout from a single reference frequency fref. In the preferred embodiment of the invention, the synthesizer 10 comprise the means for generating the transmitter and/or receiver local oscillator frequency for a mobile or a portable communication unit (not shown), such as a two-way radio. The synthesizer 10 includes a reference oscillator 11 for generating an oscillation frequency Fosc. In the preferred embodiment of the invention the reference oscillator 11 comprises a crystal oscillator having an oscillator frequency Fosc=16.8 MHZ. The oscillator output is applied to programmable fractional reference divider 12 which provides the reference frequency fref for the synthesizer 10. The fractional reference divider 12 divides the oscillator frequency Fosc by a programmable reference divisor R to provide reference frequency fref. Accordingly, Fosc = R* fref.

A phase detector 13 compares the phase difference between the output of fractional reference divider 12 and output of a programmable divider 16 and provides a phase error voltage or current according thereto. The phase error voltage is coupled to a voltage controlled oscillator (VCO) 15 via a low pass filter 14. The VCO locks to a desired output frequency fout, when no phase error exists between the inputs of the phase detector 13. The output of the VCO 14 is connected to the programmable divider 16. The output of the programmable divider 16 has a divider frequency fd which as well as being applied to the phase detector 13 provides a clock input for a signal processor 17 and a fractional loop divider 21. The signal processor 17 is connected to the programmable divider 16 which divides the output frequency fout by a loop divisor K. The loop divisor K is a ratio by which the output frequency fout is divided and compared to the fref and accordingly the following relationship exists between the frequency output fout and reference frequency fref: fout= K*fref.

It is well known in the art that in a fractional-N synthesizer it may be necessary to periodically adjust the loop divisor K in a manner such that the average output frequency is equal to the desired output frequency fout. In the preferred embodiment of the invention, the frequency synthesizer 10 is capable of providing an FM modulated output frequency fout. The modulation of the output frequency is accomplished by a phase modulation technique in which the loop divisor K is varied with time as a function of a modulating signal 9 and a fractional modulus J. The signal processor 17 receives the fractional modulus J form a fractional loop divider 21 and modulates it in accordance with a digital representation of the modulating signal 9 provided by an analog to digital converter (A/D converter) 18. The phase modulation is achieved by introducing to the loop divisor K a variation which is a function of the instantaneous amplitude of the modulating signal 9. The variation in loop divisor K causes a phase perturbation in the loop. The perturbation in the loop can be measured at the output of the VCO 15 as variation in frequency proportional to the amplitude of the modulating signal 9. It is well known that a PLL circuit attenuates frequency components of the modulating signal above the PLL unity gain frequency. Therefore, the modulating signal 9 must be additionally applied to the VCO 15 if frequency components of the modulating signal exceed the unity gain frequency of the PLL. This technique is known as two spot modulation. Accordingly, the VCO 14 may receive a modulating signal 9 that directly modulates the VCO using well known techniques, such as direct frequency modulation (FM). As will be described below, the signal processor 17 includes means for modulating the fractional modulus J in accordance with the the modulating signal 9. The A/D convertor 18 is clocked in by a sampling signal 19 at an arbitrary rate fs.

The fractional loop divider 21 comprises a programmable fractional divider identical to the fractional divider described in Martin, U.S. patent No. 4,816,774 titled "Frequency Synthesizer with Spur compensation" and assigned to the assignee of the present invention which is hereby incorporated by reference. The fractional loop divider 21 may be programmed via a controller 22 to generate the desired fractional modulus J. The fractional modulus J is determined by the following formula: J=M+N/D

where:

   M=integer divider

   N=fractional numerator

   D=fractional denominator.

One of ordinary skill in the art will appreciate that the fractional denominator D sets minimum frequency steps by which the output frequency fout may be incremented. The frequency steps are therefor determined by the ratio of fref/D. It is well known that in radio communication applications where the synthesizer 10 is utilized as a local oscillator, the frequency steps determine the achievable channel spacing of the communication system. In this applications the frequency step must be an integer multiple of the channel spacing. For example, in a communication system having a 25 kHz channel spacing, the frequency steps may comprise 1, 1.25, 5, 6.25, 12.5 or 25 kHz.

The controller 22 comprise any well known microcomputer, such as a MC68HC11 family of microcomputers manufactured by Motorola Inc. The controller 22 provides the reference divisor R for the fractional reference divider 12. In the preferred embodiment of the invention the fractional reference divider 12 comprise a fractional divider similar to the fractional divider of fractional loop divider 21. The reference divider R may assume one of a predetermined number of integer or fractional values.

The fractional numerator N comprises the number of frequency steps by which the output frequency is incremented from M* fref. Accordingly if the desired frequency output fout is a integer multiple of reference frequency fref then fractional numerator N is equal to zero. Preferably, an offset value could be added to the fractional numerator N to provide optimum spur characteristics for any desired output frequency fout. A memory device 23 which may comprise an electrically erasable programmable read only memory (EEPROM) is utilized to contain prestored frequency data including M,N, R and D for use by the fractional loop divider 21 so as to produce appropriate fractional modulus J for a desired output frequency fout.

The microprocessor controller 22 reads the frequency data from the memory 23 and supplies the data to the fractional loop divider 21. A frequency selector 24 is coupled to the microprocessor controller 22 for addressing the appropriate memory location which contains frequency data for the selected frequency. In applications such as two-way radios, the frequency selector may correspond to a channel switch.